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RFIC - Microstrip Transmission Line Design

2016-10-04

Microstrip transmission line is one of the basic type of transmission line in RF integrated circuit. Here is a basic/simple design example of it. This is a homework for course ECE810 RF Integrated Circuits in MSU.

To begin with

Microstrip is one kind of transmission line in the circuit. We use them to achieve impedance matching or some other application. Here are some simple design examples.

Problems

Design following transmission lines (use simplifying assumptions):

Solution

Problem 1

For RT Duroid material, use the w/h1 formula to recalculate. i.e.

Z0=120πεeff[w128+1.393+0.667ln(w128+1.44)]

This time I substitute the w=400μm (another assumption) in the εeff formula. I choose this value to get rid of the recursive calculation to find the exact value of w.

εeffεr+12+εr12[11+12h/w]=3+12+312[11+12×128/400]=2.4545

Denote C=120πZ0εeff1.393, we obtain

f(w)=w128+0.667ln(w128+1.44)C=0f(x)=x+0.667ln(x+1.44)Cf(x)=1+0.667x+1.44C

Use Newton-Raphson method to find the value w.

xi+1=xif(xi)f(xi)

and finally w128=2.9520, thus w=2.9520×128=320.5948 μm.

Problem 2

When it comes to CMOS cases, the substrate height h is usually very small, but I also assume w/h>1. Take w=15 μm to calculate the efficient ε.

εeffεr+12+εr12[11+12h/w]=4.1+12+4.112[11+12×10/15]=3.0667

Go through the similar process above, it is not hard to calculate that C1=2.9125, and wh=2.0746, which returns w1=20.7459 μm. This result is close to the value we used to calculate εeff, so there is no need to redesign again.

Problem 3

For the CMOS case with substrate height h=5 μm, similarly first calculate the efficient εeff.

εeffεr+12+εr12[11+12h/w]=4.1+12+4.112[11+12×5/8]=3.0816

And C2=2.9021, wh=2.0658w=10.3289 μm.

Problem 4

Z0 increases with h and decreases with w and εr. When the minimum allowable wmin=2 μm,

εeffεr+12+εr12[11+12h/w]=4.1+12+4.112[11+12×12]=2.980

When h=10 μm,

Z0,max=120πεeff[wh+1.393+0.667ln(wh+1.44)]=120π2.98[210+1.393+0.667ln(210+1.44)]=113.5691 Ω.

When h=5 μm,

Z0,max=120π2.98[25+1.393+0.667ln(25+1.44)]=96.7805 Ω

That is the highest characteristic impedance we can achieve with the CMOS.

Problem 5

As demonstrated above, Z0 increases with h and decreases with w and εr. We need to lower the substrate height h and increase microstrip width w and εr. Let’s choose a substrate material, say GaAs, and εr=12.7.

εeffεr+12+εr12[11+12h/w]=12.7+12+12.712[11+12×12]=9.0611

More detailedly, it is the ratio w/h that matters. For here, I choose w/h=2.

Z0,max=120π9.0611[21+1.393+0.667ln(21+1.44)]=29.6983 Ω

Further, if I increase the ratio to w/h=5, we can calculate that Z0=16.4027 Ω. This is lower than the previous case.

I don’t know whether there is a theoretical limitation for the w/h ratio, but in practical application when w is too high, there will be less space for other components. Also, a rule of thumb is that we need to limit the thickness of the microstrip substrate to 10% of a wavelength.

Simulation result

lineCalc result in ADS (Advanced Design System, a keysight software):

(Follow the instruction in this video.)



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